With the development of the semiconductor technology, requirements for the feature size and performance of CMOSFET (Complementary Metal Oxide Semiconductor Field Effect Transistor) devices are increasing continuously. The application of the strained channel technology to the MOSFETs can improve device performance. For example, it is possible to enhance the carrier mobility by applying stress to the channel between the source and drain, so as to improve the performance of Integrated Circuits. Specifically, for an nMOSFET, the carriers in the channel are electrons, and a tensile stress across the channel can improve the mobility of the electrons; while for a pMOSFET, the carriers in the channel are holes, and a compressive stress across the channel can improve the mobility of the holes.
However, due to the increased density and reduced pitch of the Integrated Circuits, it is more difficult for the strained channel to provide sufficient stress to satisfy the requirements for device performance.
In view of this, there is a need for a novel semiconductor structure and a method for manufacturing the same to further enhance the channel stress.